About

EEE graduate working across embedded systems and VLSI — firmware and PCB design, transistor-level analog design with SPICE simulation and DRC/LVS in Cadence Virtuoso, and RTL design with UVM-based verification. I use Python and object-oriented programming to automate simulation and verification.

Experience

Embedded System Engineer (R&D)
Ulterior Engineering Intl.
Mohakhali, Dhaka · Sep 2026 – Present
- Research and development on multiple MCUs and firmware development for optimized client solutions.
- Schematic and PCB design for customized modules; component soldering.
- STM32
- PCB design
- FPGA
- Firmware development
- Communication protocols
Software Engineer
Ekagra Health Inc. (opens in new tab)
Remote, US-based · Jul 2025 – Aug 2026
- Architected and maintained EHR software using object-oriented design patterns, building modular, reusable class hierarchies for scalability and long-term maintainability.
- Developed an AI-assisted clinician workflow, integrating Scribing and Wound Care models into the EHR to automate clinical tasks.
- Led a team of 4 engineers, working with clinical product stakeholders to turn requirements into technical specs.
- Python
- Object-oriented programming
- System architecture design

Skills

Analog design

Transistor-level design
Two-stage op-amps
StrongARM comparators
Stick diagrams
PVT corners
SPICE (DC, AC, transient, noise)

Digital design

Verilog
SystemVerilog
RTL design
FSMs & sequential circuits
RISC-V (RV32I)
UART, SPI, I2C
APB, AHB, AXI4-Lite

Verification

SystemVerilog OOP
UVM
SVA

Embedded systems

ESP32
STM32
AVR/Arduino
ARM Cortex-M
FPGA
GPIO, interrupts, timers
PWM, ADC, DMA
FreeRTOS
Bare-metal C/C++
PlatformIO

Communication protocols

UART
SPI
I2C
RS-485
Modbus RTU/TCP
MQTT
Ethernet/TCP-IP

PCB & hardware

Altium Designer
KiCad
PCB soldering

EDA & simulation

Cadence Virtuoso (schematic, ADE)
Cadence Genus
Cadence Innovus
DRC/LVS
LTspice
Proteus
Wokwi
Icarus Verilog
ModelSim
Intel Quartus
AMD Vivado XSim
EDA Playground

Programming & tools

C
C++
Python
MATLAB
Bash
JavaScript
Linux
Git

Education

BSc in Electrical and Electronic Engineering
Major: Electronics
Ahsanullah University of Science and Technology (AUST), Dhaka
2025
HSC, Science
New Govt. Degree College, Rajshahi
2019
SSC, Science
Rajshahi Collegiate School, Rajshahi
2017

Coursework

VLSI I
CMOS networks, transmission gates, pass transistors, Elmore delay, DC and transient response, linear delay model, dynamic circuits, layout, fault analysis, stick diagrams, Cadence, Verilog
VLSI II
Physical design, floorplanning, routing (maze, dogleg, left-edge), timing analysis, KL and FM partitioning, Dijkstra's shortest path, testbenches, Genus, Innovus
Digital Logic Design
Combinational and sequential circuits, K-maps, FSMs, memory, counters
Electronic Circuits I & II
BJTs, MOSFETs, op-amps, power amplifiers, feedback amplifiers, active filters
Computer Architecture
SAP I & II, cache mapping, memory organization, pipelining
Microprocessor, Interfacing & System Design
16-bit architecture, memory organization, bus activities, instruction set, 8255, 8279, 8253 PIT
Processing & Fabrication Technology
Power Electronics
SCR, IGBT, GTO, TRIAC, UJT, DIAC, rectifiers, buck, boost and buck-boost converters
Programming Language
C++, OOP, data structures and algorithms

Certifications & training

Verification Series Part 1: SystemVerilog Essentials
Embedded Systems Essentials with Arm: Get Practical with Hardware — edX
Learning FPGA Development — LinkedIn Learning
15-day Design Verification (DV) and DFT training — Ulkasemi

Leadership & activities

Programming Team Lead (R&D)
AUST Satellite and Communication Laboratory
Apr 2023 – Apr 2024
- Experimented with an image recognition system on satellite images.
- Built a website and project management system for the lab.
Sub-Executive (Web Team)
AUST Innovation and Design Club
Apr 2023 – Apr 2024
- Automated email communication and certificate generation.
- Helped organize club workshops and events with the executive team.